A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed. | Cmos Vlsi Layout And Verification Of A Simd Computer by Jianqing Zheng, Paperback | Indigo Chapters